View FDMF4061_9068649.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

to learn more about on semiconductor, please visit our website at www.onsemi.com please note: as part of the fairchild semiconductor integration, some of the fairchild orderable part numbers will need to change in order to meet on semiconductors system requirements. since the on semiconductor product management systems do not have the ability to manage part nomenclature that utilizes an underscore (_), the underscore (_) in the fairchild part numbers will be changed to a dash (-). this document may contain device numbers with an underscore (_). please check the on semiconductor website to verify the updated device numbers. the most current and up-to-date ordering information can be found at www.onsemi.com . please email any questions regarding the system integration to fairchild_questions@onsemi.com . is now part of on semiconductor and the on semiconductor logo are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries in the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of on semiconductors product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does on semiconductor assume any liability arising out of the application or use of any product or circuit, and specifcally disclaims any and all liability, including without limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. typical parameters which may be provided in on semiconductor data sheets and/or specifcations can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer application by customers technical experts. on semiconductor does not convey any license under its patent rights nor the rights of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classifcation in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its offcers, employees, subsidiaries, affliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affrmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner.
? 2016 fairchild semiconductor corporation www.fairchildsemi.com FDMF4061 rev.1.0 1 fdm 4061 - high performance 60 v smart power stage module FDMF4061 C high performance 60 v smart power stage module features ? compact size C 6. 0 mm x 7. 5 mm pqfn ? high current handling : 25a ? next generation 60v power mosfets: ? typ. r ds(on) =2.4(hs) / 2.4(ls) m? at v gs =10v, i d =25 a ? wide driver power supply voltage range : 10v to 20v ? internal pull-down resistors for pwm inputs (hi,li) ? short pwm propagation delays ? under-voltage lockout (uvlo) ? fu lly optimized system efficiency ? high performance low profile package ? integrated 60 v half-bridge gate driver ? fairchild 60v powertrench? mosfets for clean switching waveforms and reduced ringing ? low inductance and low resistance packaging for minimal operating power losses ? fairchild g reen packaging and rohs compliant ? reduced emi due to low side flip-chip mosfet general description the FDMF4061 is a compact 60v smart power stage (sps) module that is a fully optimized for use in high curre nt switching applications. the FDMF4061 module integrates a driver ic plus two n-channel power mosfet s into a thermally enhanced, 6 .0 mm x 7. 5 mm pqfn package. the pqfn packaging provides very low package inductance and resistance improving the current handling capability and performance of the part. with an integrated approach, the complete switching power stage is optimized with regards to driver and mosfet dynamic performance, system parasitic inductance, and power mosfet r ds(on) . the FDMF4061 uses fairchild's high performance powertrench tm mosfet technology, which reduces high voltage and current stresses in switching applications. the driver ic features a low de lay times and matched pwm input propagation delays , which further enhance the performance of the part. applications ? motor drives (power tools & drowns etc.) ? telecom half / full - bridge dc -dc converters ? buck-boost converters ? high-current dc-dc point of load (pol) converters. application diagram ordering information part number current rating [a ] input voltage [ v ] frequency max [ khz ] device marking FDMF4061 25 60 200 FDMF4061 september 2016 hi li hb ph vin sw ho hg vdd ho lg vss pgnd vdd vin mcu c boot r gh r gl c vin FDMF4061 m r boot d boot
? 201 6 f airchild semiconductor corporation www.fairchildsemi.com FDMF4061 rev.1.0 2 fdm 4061 - high performance 60 v smart power stage module functional block diagram figure 1 . functional block diagram pin configuration figure 2 . pin configuration ( 6 .0 mm x 7 .5 mm package) l i v d d v i n v s s s w h o h i q 1 p o w e r m o s f e t ( h i g h s i d e ) q 2 p o w e r m o s f e t ( l o w s i d e ) p g n d l o h b p h u v l o u v l o l e v e l s h i f t h g l g v d d 5 0 0 k 5 0 0 k l g b o o t 2 3 4 h o v i n p g n d p g n d 3 3 3 5 3 6 5 6 7 l g p g n d s w s w s w s w s w s w s w s w s w s w v i n v i n p g n d p g n d v d d p h v i n v i n 8 9 t o p v i e w l o p g n d h g 3 2 2 8 3 1 2 6 2 7 l i h i n / c v s s 1 0 1 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 p g n d 3 7 n / c n / c 2 9 3 4 n / c 3 0
? 201 6 f airchild semiconductor corporation www.fairchildsemi.com FDMF4061 rev.1.0 3 fdm 4061 - high performance 60 v smart power stage module p in definitions pin name function 1, 29, 32, 34 n/c no connect 2 vdd power supply input for low - side gate drive and bootstrap diode. bypass this pin to vss with a low impedance capacitor. 3 hi high - side pwm input. 4 li low - side pwm input. 5, 10,11, 22, 23, 33, 37 pgnd power return for the power stage. package header, p in 37 and pgnd are internally fused (shorted). 6 vss analog ground for driver ic analog circuits. 7,9 lg low - side mosfet gate. 8 lo low - side gate drive output. 1 2 - 2 1 sw switching node junction between high - side and low - side mosfets. 24 - 28 vin power input for the power stage. bypass this pin to pgnd with low impedance capacitor. 30 hg high - side mosfet gate. 31 ph high - side source connection (sw node) for the bootstrap capacitor . 35 hb bootstrap supply for high - side driver. bypass this pin to ph with low impedance capacitor. 36 ho high - side gate drive output. table 1 . pin definitions
? 201 6 f airchild semiconductor corporation www.fairchildsemi.com FDMF4061 rev.1.0 4 fdm 4061 - high performance 60 v smart power stage module typical application diagram figure 3 . half - bridge dc motor figure 4 . full - bridge dc motor h i l i h b p h v i n s w l o h g v d d h o l g v s s p g n d v d d v i n m c u c b o o t r g h r g l c v i n f d m f 4 0 6 1 m r b o o t d b o o t h i l i h b p h v i n s w l o l g v d d h o h g v s s p g n d v d d v i n m c u c b o o t 2 r g h 2 r g l 2 c v i n 2 f d m f 4 0 6 1 h i l i h b p h v i n s w l o l g v d d h o h g v s s p g n d v d d c b o o t 1 r g h 1 r g l 1 f d m f 4 0 6 1 v i n c v i n 1 m c v d d 1 c v d d 2 r b o o t 1 d b o o t 2 r b o o t 1 d b o o t 1
? 201 6 f airchild semiconductor corporation www.fairchildsemi.com FDMF4061 rev.1.0 5 fdm 4061 - high performance 60 v smart power stage module typical application diagram (continued) figure 5 . 3 - phase dc motor h i l i h b p h v i n s w l o l g v d d h o h g v s s p g n d v d d v i n m c u c b o o t 3 r g h 3 r g l 3 c v i n 3 f d m f 4 0 6 1 h i l i h b p h v i n s w l o l g v d d h o h g v s s p g n d v d d c b o o t 2 r g h 2 r g l 2 f d m f 4 0 6 1 v i n c v i n 2 h i l i h b p h v i n s w l o l g v d d h o h g v s s p g n d v d d c b o o t 1 r g h 1 r g l 1 f d m f 4 0 6 1 v i n c v i n 1 m c v d d 3 c v d d 2 c v d d 1 r b o o t 1 d b o o t 1 r b o o t 2 d b o o t 2 r b o o t 3 d b o o t 3
? 201 6 f airchild semiconductor corporation www.fairchildsemi.com FDMF4061 rev.1.0 6 fdm 4061 - high performance 60 v smart power stage module typical application diagram (continued) figure 6 . buck converter figure 7 . half - bridge converter typical application diagram (continued) h i l i h b p h v i n s w l o l g v d d h o h g v s s p g n d v d d v i n p w m c o n t r o l l e r c b o o t r g h r g l c v i n f d m f 4 0 6 1 r l o a d l o u t c o u t r b o o t d b o o t h i l i h b p h v i n s w l o l g v d d h o h g v s s p g n d v d d v i n s e c o n d a r y s i d e c i r c u i t p w m c o n t r o l l e r c b o o t r g h r g l c v i n 1 c v i n 2 f d m f 4 0 6 1 r b o o t d b o o t
? 201 6 f airchild semiconductor corporation www.fairchildsemi.com FDMF4061 rev.1.0 7 fdm 4061 - high performance 60 v smart power stage module figure 8 . full - bridge converter h i l i h b p h v i n s w l o l g v d d h o h g v s s p g n d v d d v i n s e c o n d a r y s i d e c i r c u i t p w m c o n t r o l l e r c b o o t 2 r g h 2 r g l 2 c v i n 2 f d m f 4 0 6 1 h i l i h b p h v i n s w l o l g v d d h o h g v s s p g n d v d d c b o o t 1 r g h 1 r g l 1 f d m f 4 0 6 1 v i n c v i n 1 c v d d 1 c v d d 2 r b o o t 1 d b o o t 1 r b o o t 2 d b o o t 2
? 201 6 f airchild semiconductor corporation www.fairchildsemi.com FDMF4061 rev.1.0 8 fdm 4061 - high performance 60 v smart power stage module absolute maximum ratings 7kh3$evroxwh0d[lpxp5dwlqjvduhwkrvhydoxhveh\rqgzklfkwkhvdihw\riwkhghylfhfdqqrwehjxdudqwhhg7khghylfhvkrxog not be operated at the se limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum ratings. the 35hfrpphqghg 2shudwlqj &rqglwlrqv wdeoh ghilqhv wkh frqglwlrqv iru actual device operation. thermal resistance rating is measured under board m ounted and still air conditions. symbol parameter min. max. unit v in power stage supply voltage referenced to vss - 0.3 6 0 v v ph ph voltage referenced to vss v hb - 25 v hb +0.3 v v dd driver supply voltage referenced to vss - 0.3 25 v v hb bootstrap to vss referenced to vss, - 0.3 85 v v li, v hi gate drive input signals referenced to vss - 0.3 v dd + 0.3v v v ho high side driver output referenced to phase v ph - 0.3v v boot + 0.3v v v lo low side driver output referenced to vss - 0.3 v dd + 0.3v v v hg high side mosfet gate referenced to phase - 2 6 28 v v lg low side mosfet gate referenced to vss - 2 6 28 v 4 ja junction to ambient thermal resistance q1 (1) - 17 c/w junction to ambient thermal resistance q 2 (1) - 15 c/w t j junction temperature - 150 c t stg storage temperature - 40 150 c table 2 . module absolute maximum ratings (1) mounted on a 4 - layer fr4 pcb with a dissipating copper surface on the top side of 49 cm2 , 2oz. recommended operating conditions symbol parameters test condition min max unit v in power stage supply voltage 3 50 v v dd driver supply voltage 10 20 v v sw , v ph sw or phase dc - 0.3 60 v repetitive pulse (< 20ns, 10uj) 6 - v dd 60 v v hb voltage on hb reference to ph v ph + 10 v ph + 20 v dv sw /dt voltage slew rate on sw - 50 v/ns t j operating temperature - 40 125 c table 3 . module recommended operating conditions
? 201 6 f airchild semiconductor corporation www.fairchildsemi.com FDMF4061 rev.1.0 9 fdm 4061 - high performance 60 v smart power stage module electrical specifications: v dd =v hb =15 v, v sw =v ss =0v, v in = 3 0 v , t j = + 25c unless otherwise noted. table 4 . module electrical specifications symbol parameter condition min. typ. max. unit supply currents i inq power stage quiescent current li = hi = 0v - - 1 ua i dd q driver quiescent current li = hi = 0v - 67 180 ua i ddo vdd operating current f sw = 20khz - 0.3 0.6 ma f sw = 200khz - 2.1 4.2 ma i hb q boot quiescent current li = hi = 0v - 38 120 ua i hbo boot operating current f sw = 20khz - 0.3 0.6 ma f sw = 200khz - 2.4 4.8 ma under - voltage protection v ddr, v hbr uvlo rising threshold v dd or v hb - v ph rising threshold 8.2 9. 5 10.0 v v ddf, v hbf uvlo falling threshold v dd or v hb - v ph falling threshold 7.6 8. 9 9.6 v v ddh uvlo hysteresis v dd hysterisis 0.6 - v t d_por por delay to enable ic uvlo rising to internal pwm enable - - 10 us control inputs (ttl: li, hi) v il low level input voltage v dd = 10v to 20v 1.2 - - v v ih high level input voltage - - 2.9 v v hys input voltage hysteresis - 1.0 - v r in input pull - down resistance - 468 - k : pwm input (hi,li) t lplh li to lo propagation d elays li low ? high to lo low ? high , v ih to 10% lg 100 153 300 ns t lphl li high ? low to lo high ? low , v il to 9 0% lg 100 208 300 ns t hplh hi to ho propagation d elay s hi low ? high to ho low ? high , v ih to 1 0% hg - ph 100 170 300 ns t hphl hi high ? low to ho high ? low , v il to 9 0% hg - ph 100 205 300 ns mt delay matching, hs and ls turn - on/off - - 50 ns t pw minimum input pulse width that changes the output li/hi rising to vth of q1,q2 r g =0 : 75 ns li/hi falling to vth of q1,q2 r g =0 : 130 ns high - side driver (hdrv) (vdd = vhb = 15v) i source_ ho output sourcing peak current v ho = 0 v 250 350 - m a i sink_ ho output sinking peak current v ho = 15 v 500 650 - m a t r_ hg rise time gh = 10% to 90% , r gh =0 : - 356 711 ns t f_ hg fall time gh = 90% to 10% , r gh =0 : - 151 302 ns low - side driver (ldrv) (vdd = vhb = 15v) i source_ lo output sourcing peak current v lo = 0 v 250 350 - m a i sink_ lo output sinking peak current v lo = 15 v 500 650 - m a t r_ lg rise time gl=10% to 90%, r gl =0 : - 346 692 ns t f_ lg fall time gl=90% to 10%, r gl =0 : - 142 283 ns
? 201 6 f airchild semiconductor corporation www.fairchildsemi.com FDMF4061 rev.1.0 10 fdm 4061 - high performance 60 v smart power stage module power mosfet specifications ( FDMF4061 ) t j = + 25c unless otherwise noted. symbol parameter condition min. typ. max. unit high side mosfet, q1 bv dss drain - source breakdown voltage i ds =250ua, v gs =0v 60 - - v i dss zero gate voltage drain current v ds = 48v , v gs =0v - - 1 ua i gss gate - source leakage current v ds =0v, v gs =+/ - 20v - - 100 na v gs(th) gate - source threshold voltage v ds =v gs , i ds =250ua 2. 5 3.7 4. 5 v r ds(on) drain source on - resistance v gs =10v, i ds =2 5 a - 2.4 3.2 p q g total gate charge v gs =0v to 10v, v dd = 3 0v, i ds =2 5 a - 56 78 nc q gs gate - source charge - 23 - nc q gd gate - 'udlq30loohu&kdujh - 8 - nc q oss total output charge - 65 - nc r g series gate resistance - 1.0 - drain - source diode characteristics v sd source to drain forward voltage v hg - v ph =0v, i sd = 2a - 0. 7 1.2 v v hg - v ph =0v, i sd = 2 5 a - 0.8 1.3 t rr reverse recovery time i f = 2 5 a, di f /dt = 100a/us - 58 117 ns q rr reverse recovery charge - 51 103 nc t rr reverse recovery time i f = 2 5 a, di f /dt = 300 a/us - 44 88 ns q rr reverse recovery charge - 79 158 nc low side mosfet, q2 bv dss drain - source breakdown voltage i ds =250ua, v gs =0v 60 - - v i dss zero gate voltage drain current v ds = 48v , v gs =0v - - 1 ua i gss gate - source leakage current v ds =0v, v gs =+/ - 20v - - 100 na v gs(th) gate - source threshold voltage v ds =v gs , i ds =250ua 2. 5 3.5 4. 5 v r ds(on) drain source on - resistance v gs =10v, i ds =2 5 a - 2.4 3.2 p q g total gate charge v gs =0v to 10v, v dd = 30 v , i ds =2 5 a - 59 82 nc q gs gate - source charge - 2 5 - nc q gd gate - 'udlq30loohu&kdujh - 11 - nc q oss total output charge - 63 - nc r g series gate resistance - 1.0 - drain - source diode characteristics v sd source to drain forward voltage v hg - v ph =0v, i sd = 2a - 0. 7 1.2 v v hg - v ph =0v, i sd = 2 5 a - 0.8 1.3 t rr reverse recovery time i f = 2 5 a, di f /dt = 100a/us - 57 114 ns q rr reverse recovery charge - 52 105 nc t rr reverse recovery time i f = 2 5 a, di f /dt = 300 a/us - 43 86 ns q rr reverse recovery charge - 81 161 nc table 5 . FDMF4061 mosfet electrical specifications
? 201 6 f airchild semiconductor corporation www.fairchildsemi.com FDMF4061 rev.1.0 11 fdmf 4061 - high performance 6 0v smart power stage module typical performance characteristics tj = 25c unless otherwise noted. figure 9 . i ddq vs. supply voltage (v dd ) figure 10 . i ddq vs. temp. figure 11 . . i hb q vs. supply voltage (v dd ) figure 12 . i hb q vs. temp. figure 13 . turn - on propagation delay vs. supply voltage(v dd ) figure 14 . turn - on propagation delay vs. t emp. 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 i ddq [ a] supply voltage [v] 45 50 55 60 65 70 75 80 85 90 95 - 40 - 20 0 20 40 60 80 100 120 i ddq [ a] temperature [ ] 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 i hbq [ a] supply voltage [v] 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 - 40 - 20 0 20 40 60 80 100 120 i hbq [ a] temperature [
? 201 6 f airchild semiconductor corporation www.fairchildsemi.com FDMF4061 rev.1.0 12 fdmf 4061 - high performance 6 0v smart power stage module typical performance characteristics (continued) tj = 25c unless otherwise noted. figure 15 . turn - off propagation delay vs. supply voltage(v dd ) figure 16 . turn - off propagation delay vs. temp. figure 17 . turn - on rising time vs. supply voltage(v dd ) figure 18 . turn - on rising time vs. temp. figure 19 . turn - off falling time vs. supply voltage(v dd ) figure 20 . turn - off falling time vs. temp. 100 125 150 175 200 225 250 275 300 10 12 14 16 18 20 turn - off propagation delay [ns] supply voltage [v] 125 150 175 200 225 250 275 300 - 40 - 20 0 20 40 60 80 100 120 turn - off propagation delay [ns] temperature [
? 201 6 f airchild semiconductor corporation www.fairchildsemi.com FDMF4061 rev.1.0 13 fdmf 4061 - high performance 6 0v smart power stage module typical performance characteristics (continued) tj = 25c unless otherwise noted. figure 21 . output sourcing current vs. supply voltage (v dd ) figure 22 . output sourcing current vs. temp. figure 23 . output sinking current vs. supply voltage (v dd ) figure 24 . output sinking current vs. temp. figure 25 . high - level output voltage d eviation from the v bh ( v dd ) vs. supply voltage ( v dd ) figure 26 . high - level output voltage d eviation from the v bh ( v dd ) vs. temp. 180 200 220 240 260 280 300 320 340 360 380 400 420 440 460 480 500 10 12 14 16 18 20 output sourcing current [ma] supply voltage [v] 260 280 300 320 340 360 380 400 420 440 - 40 - 20 0 20 40 60 80 100 120 output sourcing current [ma] temperature [
? 201 6 f airchild semiconductor corporation www.fairchildsemi.com FDMF4061 rev.1.0 14 fdmf 4061 - high performance 6 0v smart power stage module typical performance characteristics (continued) tj = 25c unless otherwise noted. figure 27 . low - level output voltage d eviation from the v p h ( v ss ) vs. supply voltage ( v dd ) figure 28 . low - level output voltage d eviation from the v p h ( v ss ) vs. temp. figure 29 . v dd uvlo threshold voltage vs. temp. figure 30 . v hb uvlo threshold voltage vs. temp. figure 31 . in+ in - vs. supply voltage . figure 32 . input logic threshold voltage vs. temp. 120 130 140 150 160 170 180 190 200 10 12 14 16 18 20 v ol [mv] supply voltage [v] 90 110 130 150 170 190 210 230 - 40 - 20 0 20 40 60 80 100 120 v ol [mv] temperature [
? 201 6 f airchild semiconductor corporation www.fairchildsemi.com FDMF4061 rev.1.0 15 fdmf 4061 - high performance 6 0v smart power stage module typical performance characteristics (continued) tj = 25c unless otherwise noted. figure 33 . static soa , v in =50v figure 34 . static soa , v in =40v figure 35 . module power loss vs. t dead figure 36 . module power loss vs. v gs figure 37 . output current vs. carrier or modulation frequency 0 5 10 15 20 25 30 35 40 45 40 80 120 160 200 module output current, i out [a] switching frequency, f sw [khz] 50vi25vo10vg 50vi25vo16vg 0 5 10 15 20 25 30 35 40 45 50 40 80 120 160 200 module output current, i out [a] switching frequency, f sw [khz] 40vi20vo10vg 40vi20vo16vg 6.0 6.5 7.0 7.5 8.0 30 60 90 120 150 module power loss, pl mod [w] dead - time [ns] 0 2 4 6 8 10 10 12 14 16 18 module power loss, pl mod [w] gate voltage [v] 30 32 34 36 38 40 42 44 46 48 50 10 100 output current[a] carrier frequency [khz] v in = 50 v , v dd = 10v , 16v v out = 25v, tj
? 201 6 f airchild semiconductor corporation www.fairchildsemi.com FDMF4061 rev.1.0 16 fdmf 4061 - high performance 6 0v smart power stage module typical performance characteristics ( q1 n - channel ) tj = 25c unless otherwise noted. figure 38 . on region characteristics figure 39 . normalized on - resistance vs. drain current and gate voltage figure 40 . normalized on resistance vs. junction temperature figure 41 . on - resistance vs. gate to source voltage figure 42 . transfer characteristics figure 43 . source to drain diode forward voltage vs. source current 4 6 8 10 0 10 20 30 40 50 t j = 125 o c i d = 25 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max 2 3 4 5 6 7 8 9 10 0 30 60 90 120 150 180 t j = 150 o c v ds = 5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.001 0.01 0.1 1 10 100 180 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) 0.0 0.5 1.0 1.5 2.0 0 30 60 90 120 150 180 v gs = 6 v v gs = 5 v v gs = 8 v pulse duration = 80 p s duty cycle = 0.5% max v gs = 10 v i d , drain current (a) v ds , drain to source voltage (v) 0 30 60 90 120 150 180 0 2 4 6 8 10 v gs = 8 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 10 v v gs = 6 v -75 -50 -25 0 25 50 75 100 125 150 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 i d = 25 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c )
? 201 6 f airchild semiconductor corporation www.fairchildsemi.com FDMF4061 rev.1.0 17 fdmf 4061 - high performance 6 0v smart power stage module typical performance characteristics ( q1 n - channel ) tj = 25c unless otherwise noted. figure 44 . gate charge characteristics figure 45 . capacitance vs. drain to source voltage figure 46 . maximum continuous drain current vs. case temperature figure 47 . forward bias safe operating area figure 48 . single pulse maximum power dissipation 0 10 20 30 40 50 60 0 2 4 6 8 10 i d = 25 a v dd = 40 v v dd = 30 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 20 v 0.1 1 10 60 1 10 100 1000 10000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss 25 50 75 100 125 150 0 20 40 60 80 100 r t jc = 3.42 o c/w v gs = 10 v i d , drain current (a) t c , case temperature ( o c ) 0.1 1 10 100 0.1 1 10 100 1000 curve bent to measured data 10 us dc 10 ms 1 ms 100 us i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r t jc = 3.42 o c/w t c = 25 o c 10 -5 10 -4 10 -3 10 -2 10 -1 1 1 10 100 1000 10000 100000 single pulse r t jc = 3.48 o c/w t c = 25 o c p ( pk ) , peak transient power (w) t, pulse width (sec)
? 201 6 f airchild semiconductor corporation www.fairchildsemi.com FDMF4061 rev.1.0 18 fdmf 4061 - high performance 6 0v smart power stage module typical performance characteristics ( q1 n - channel ) tj = 25c unless otherwise noted. figure 49 . junction - to - case transient thermal response curve 10 -5 10 -4 10 -3 10 -2 10 -1 1 0.001 0.01 0.1 1 2 single pulse duty cycle-descending order r(t), normalized effective transient thermal resistance t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01
? 201 6 f airchild semiconductor corporation www.fairchildsemi.com FDMF4061 rev.1.0 19 fdmf 4061 - high performance 6 0v smart power stage module typical performance characteristics ( q2 n - channel ) tj = 25c unless otherwise noted. figure 50 . on - region characteristics figure 51 . normalized on - resistance vs. drain current and gate voltage figure 52 . normalized on resistance vs. junction temperature figure 53 . on - resistance vs. gate to source voltage figure 54 . transfer characteristics figure 55 . source to drain diode forward voltage vs. source current 0.0 0.2 0.4 0.6 0.8 1.0 0 40 80 120 160 200 v gs = 6 v v gs = 8 v pulse duration = 80 p s duty cycle = 0.5% max v gs = 10 v i d , drain current (a) v ds , drain to source voltage (v) 0 50 100 150 200 0 5 10 15 20 v gs = 8 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 10 v v gs = 6 v -75 -50 -25 0 25 50 75 100 125 150 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 i d = 25 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) 4 5 6 7 8 9 10 0 10 20 30 40 50 t j = 125 o c i d = 25 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max 3 4 5 6 7 8 9 0 40 80 120 160 200 t j = 150 o c v ds = 5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.001 0.01 0.1 1 10 100 200 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v)
? 201 6 f airchild semiconductor corporation www.fairchildsemi.com FDMF4061 rev.1.0 20 fdmf 4061 - high performance 6 0v smart power stage module typical performance characteristics ( q2 n - channel ) tj = 25c unless otherwise noted. figure 56 . gate charge characteristics figure 57 . capacitance vs. drain to source voltage figure 58 . maximum continuous drain current vs. case temperature figure 59 . forward bias safe operating area figure 60 . single pulse maximum power dissipation 10 -5 10 -4 10 -3 10 -2 10 -1 1 1 10 100 1000 10000 100000 single pulse r t jc = 3.48 o c/w t c = 25 o c p ( pk ) , peak transient power (w) t, pulse width (sec) 0 12 24 36 48 60 0 2 4 6 8 10 i d = 25 a v dd = 40 v v dd = 20 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 30 v 0.1 1 10 60 1 10 100 1000 10000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss 25 50 75 100 125 150 0 20 40 60 80 100 r t jc = 3.48 o c/w v gs = 10 v i d , drain current (a) t c , case temperature ( o c ) 0.1 1 10 100 0.1 1 10 100 1000 curve bent to measured data 10 us dc 10 ms 1 ms 100 us i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r t jc = 3.48 o c/w t c = 25 o c
? 201 6 f airchild semiconductor corporation www.fairchildsemi.com FDMF4061 rev.1.0 21 fdmf 4061 - high performance 6 0v smart power stage module typical performance characteristics ( q2 n - channel ) tj = 25c unless otherwise noted. figure 61 . junction - to - case transient thermal response curve 10 -5 10 -4 10 -3 10 -2 10 -1 1 0.001 0.01 0.1 1 2 single pulse duty cycle-descending order r(t), normalized effective transient thermal resistance t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01
? 201 6 f airchild semiconductor corporation www.fairchildsemi.com FDMF4061 rev.1.0 22 fdmf 4061 - high performance 6 0v smart power stage module functional description the FDMF4061 is a non - inverting 6 0v half - bridge smart power stage (sps) module. the module packages a driver ic die along with pair of equally sized (matched r dson ) 6 0v powertrench tm n - channel mosfets (standard gate thresholds refer to table 5 ) . the FDMF4061 module provides separate power input pins; the power stage input (vin) and the gate driver input (vdd). the power stage input (vin) accepts a wide operating from 3v to 5 0v , while the gate driver input ( vdd ) requires 10v to 20v. the module accepts ttl compatible inputs (hi/li) along with anti - cross conduction circuitry to protect against over - lapping pwm (hi/li) pulses. the module (driver ic) also implements uvlo circuitry in both the vdd - vss and boot - ph power domains. power - up an d uvlo operation uvlo circuits are implemented in both the vdd - vss and hb - ph power domains. during power - up, the vdd - vss uvlo circuit forces ho and lo low until the vdd supply voltage exceeds the uvlo rising threshold ( 9.2 v typ.). the module (driver ic) will begin responding to pwm pulses once vdd exceeds the uvlo threshold. the uvlo circuit does contain hysteresis (~0.6v) to prevent noise from interfering with normal operation. an additional uvlo circuit is implemented on the hb - ph pins which will hold h o low until hb - ph > ( 9.2 v typ.). the hb - ph uvlo also incorporates hysteresis (~0.6v). vdd uvlo boot uvlo driver state 0 x disabled (g h , gl=0) 1 0 gl follows pwm , gh=0) 1 1 enabled (gh/gl follow pwm ) table 6 . uvlo truth table figure 62 . min/max uvlo thresholds pwm input stage the FDMF4061 incorporates a pwm input gate drive design, where the low side drive output (lo) and high side drive output (ho) are controlled through independent pwm inputs (li and hi, respectively). the module (driver ic) can be used with ttl compatible input signals . the input signals can also be driven with voltage levels that are lower than the vdd supply level. the vdd supply level does not affect the input threshold levels (vih and vil). figure 63 . pwm thresh old definitions - v ih = pwm trip level to flip state from low to high. - v il = pwm trip level to flip state from high to low. d r i v e r o u t p u t s t a t e ( h o / l o ) 1 0 . 0 7 . 6 v d d - v s s , b o o t - p h ( v o l t s ) d i s a b l e d e n a b l e d v i h v i l h g / l g h i / l i
? 201 6 f airchild semiconductor corporation www.fairchildsemi.com FDMF4061 rev.1.0 23 fdmf 4061 - high performance 6 0v smart power stage module driver output stage the driver ic output stage is designed to drive a pair of n - channel mosfets. the driver outputs (lo, ho) are non - inverting and will follow the pwm input commands (li, hi respectively). the lo and ho outputs are capable of sinking and sourcing up to 0.65/0.35a peak current respectively. the driver output stage is also capable of providing a rail (vdd) to rail ( vss ) output voltage level when driving the power mosfets. depending on the end application, the output voltage level can be set to aide in optimizing mosfet and driver ic power losses. the driver output voltage level can also be used to help adjust sw nod e edge rates. timing diagram figure 64 . pwm timing diagram (li / hi signals) h o h i t r _ g h t h p l h t f _ g h 1 0 % s w 9 0 % t h p h l l o l i t r _ g l t l p l h t f _ g l 1 0 % 9 0 % t l p h l
? 201 6 f airchild semiconductor corporation www.fairchildsemi.com FDMF4061 rev.1.0 24 fdmf 4061 - high performance 6 0v smart power stage module application information: the FDMF4061 is designed as a non - inverting power stage, where the power mosfet response (sw node) is designed to follow to hi/li commands. the device is well - suited to be used in a wide variety of applications, such as: half and full - bridge dc - dc converters, active c lamp forward converters, rectifier circuits, and motor drive power stages. however, various applications and topologies can place unique stresses on the module. there are a few basic power - stage requirements needed to ensure proper operation . module power dissipation as previously mentioned, the FDMF4061 is a multi - chip module (mcm). the module consists of three die (hs mosfet, ls mosfet and driver ic). each die dissipates heat in normal operation resulting from power loss. the power mosfets can generate p ower loss from conduction and switching losses while the driver ic dissipated loss from bias, boot diode conduction and from the driver output stage sinking and sourcing power mosfet gate currents and operating frequency . the amount of heat dissipated by a ny die is largely dependent o n the operating conditions. the close physical placement of the three die inside of the package translates into strong thermal coupling between die. ideally, a thermal camera should be used to monitor the FDMF4061 during the en gineering development phase. this can help ensure the module operates within the absolute maximum ratings specified in this datasheet. operating modes the FDMF4061 can reliably operate while driving various load impedances. however, the relatively large number of applications can result in the module operating in various modes. common applications such as switching power converters and motor drives can place the FDMF4061 into different operating modes. the various operating modes will change the response of the mosfet voltage and current stresses and power losses as well as the gate driver dead time response. a few operating modes are listed below. h - bridge motor drive in this operating mode, it allows bi - directional current flow through motor by enabling dia gonal mosfets to make current flow in one or the other direction. inductor current will not tolerate abrupt changes either when charged or discharged and alternat e p ath is required to protect switches during dead - time. the path can be made either mosfet body - diode conducting as soon as switches are disabled or enabling opposite high - side or low - side switch to carry the recirculation current while avoiding shoot - throug h. utilizing mosfet channel is often much more efficient way to handle the decaying current due to lower conduction power loss than body - diode forward drop loss. figure 65 . h - bridge motor drive FDMF4061 power dissipation the maximum motor drive current can be obtained from estimating total power dissipation of motor driver. there are a number of factors which limit actual current level such as motor ratting, driver ic, pcb construction, ambient t emperature and given application. all of power dissipation components must be considered to get reliable operation at the specific application. there is obvious power dissipations listed below in single h - bridge motor application. ? conduction loss genera lly biggest power loss which is dissipated due to the r dson and its temperature coefficient must be considered in the calculation p g n d f d m f 4 0 6 1 s w q 1 q 2 v i n s w q 1 q 2 f d m f 4 0 6 1 f o r w a r d d r i v e r e v e r s e d r i v e d e a d - t i m e ( b o d y - c o n d u c t i o n ) 2 out ls_temp - ds(on) hs_temp - ds(on) cond i ) r (r p ?
? 201 6 f airchild semiconductor corporation www.fairchildsemi.com FDMF4061 rev.1.0 25 fdmf 4061 - high performance 6 0v smart power stage module ? switching losses - rising and falling time by parasitic inductance can be measured in the application, listed below assumed zero inductance. switching off loss switching on loss ? gate drive loss ? quiescent current power loss current is still drawn from the vdd and hb pins for internal and level shifting circuitry without load ( r g =open). power loss by quiescent current is ? supply current power loss(r g =0 ? h i l i h b p h v i n l o l g v d d h o h g v s s p g n d v d d v i n p w m c o n t r o l l e r c b o o t r g h r g l c v i n f d m f 4 0 6 1 r l o a d l f i l t e r c o u t v o u t i l ( a ) 0 a i l t i m e s w q 1 q 2 v o u t r b o o t d b o o t ) r /(r v i ; )/i q (q t : where f ) 2 t i v ( p drv_off gh plateau g(off) g(off) gd gs2 off sw off ds(off) in sw(off) ? ? ? charge output qoss ) r /(r v i ; )/i q (q t : where f ) 2 v qoss 2 t i v ( p drv_on g plateau g(on) g(on) gd gs2 on sw in on ds(on) in sw(on) ? ? ? ? sw drv g gate f v q p ? ? hbo hb ddo dd supply i v i v p ? ? hbq hb ddq dd quiescent i v i v p ? ? supply gate sw cond total p p p p p ) p ( t t total ja a j ? 4
? 201 6 f airchild semiconductor corporation www.fairchildsemi.com FDMF4061 rev.1.0 26 fdmf 4061 - high performance 6 0v smart power stage module however, similar operation can arise when a switching converter (such as a synchronous buck) is pulling energy from the output filter capacitors and delivering the energy back to the input filter capacitors. figure 67 . synchronous boost converter operating in ccm from a module perspective, the main difference here versus the previous (buck) operating mode is that this situation will cause the ls fet (q2) to act as the control mosfet and hard switch whi le the hs fet (q1) acts as a synchronous rectifier and undergoes soft switching with body diode recovery. this type of operation can drastically change power losses dissipated in q1 and q2 versus buck operating mode. dv ds /dt control using external gate res istors the FDMF4061 also provides module pins for placing external gate resistors. the module provides pins for the ho and lo signals (driver output signals) and the hg and lg (power mosfet gate pins). resistors can be placed in series with the mosfet ga te to control the sw node edge rates. independently controlling mosfet (slower) turn - on and (faster) turn - off slew rates can also be accomplished by using the resistor and diode circuit shown in figure 68 . figure 68 . gate drive resistor - diode circuit c gd x dv ds /dt turn - on c gd x dv ds /dt turn - on is a false (unwanted) turn - on event that often creates a brief and uncontrolled shoot through current between the hs (q1) and ls (q2) mosfets. typically, a c gd x dv ds gw 3vkrrw - wkurxjk condition arises from capacitive feedback current flowing th rough c gd into c gs inducing a gate - bounce - induced channel turn - on of the mosfet. holding the gate below threshold can become challenging because the high - frequency capacitive displacement current from c gd (due to dv ds /dt) couples back to circuit ground thr ough the gate electrode. figure 69 . c gd x dv ds /dt current flow ld_ls ls_ls l g _brd l g _pack r g r drive _ls q 2 c g d c g s z gate_drv ~ r + z l z mos_gate ~ 1/ z c h i l i h b p h v i n ( p i n ) l o l g v d d h o h g v s s p g n d v d d v i n p w m c o n t r o l l e r c b o o t r g h r g l c o u t f d m f 4 0 6 1 r l o a d l f i l t e r c i n v o u t i l ( a ) 0 a i l t i m e s w q 1 q 2 v o u t r b o o t d b o o t h i l i h b p h v i n v d d h o h g v s s p g n d v d d v i n c b o o t r g h _ o n c v i n f d m f 4 0 6 1 r l o a d l f i l t e r c o u t v o u t i l s w q 1 q 2 r g h _ o f f d g h _ o f f l o l g r g l _ o n r g l _ o f f d g l _ o f f i n p u t f r o m c o n t r o l l e r r b o o t d b o o t
? 201 6 f airchild semiconductor corporation www.fairchildsemi.com FDMF4061 rev.1.0 27 fdmf 4061 - high performance 6 0v smart power stage module the gate - to - ground impedance is the parallel combination of the gate drive (z g_drv ) and the mosfet gate - to - source (z mos_gate ) paths. as dv ds /dt increases, the more favorable path for displacement current is through the capacitive gate - source (c gs ) path versus the highly inductive and resistive gate drive loop. so impedence through gate driver should be minimized. the severity of the shoot through current is difficult to predict.
? 201 6 f airchild semiconductor corporation www.fairchildsemi.com FDMF4061 rev.1.0 28 fdmf 4061 - high performance 6 0v smart power stage module physical dimensions figure 70 . clip bond pqfn 6.0mm x 7.5mm package dimensions package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and /or date on the drawing and contact a fairchild semiconductor representative to verify or obtain the most recent revision. package specifications do not expand the terms of fairchilds worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductors online packaging ar ea for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .

www. onsemi.com 1 on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 www.onsemi.com literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative ? semiconductor components industries, llc

▲Up To Search▲

Price & Availability of FDMF4061

	To Download FDMF4061 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .